1. Field of the Invention
The present invention relates to electronic systems utilizing logic signals. More particularly, the present invention provides a method for shielding signal lines which would otherwise inductively or capacitively couple to adjacent conductors.
2. The Background Art
As integrated circuit (IC) designs become more complex, and as those designs utilize higher signal frequencies, there is an increased likelihood of crosstalk between adjacent interconnect lines within one or more functional blocks in an IC.
Typical IC's include large and small functional blocks coupled together by interconnect lines.
FIG. 1 is a block diagram of a prior art IC showing megablocks and interconnect lines.
Referring to FIG. 1, integrated circuit 10 comprises megablocks 12, 14, 16, 18, and 20, each megablock being connected to other megablocks by interconnect lines 22a through 22i provided for that purpose. Each of megablocks 12, 14, 16, 18, and 20 includes logic gates, transistors, and other components. It is common for IC's to include megablocks which have rows of functional circuits, with the circuitry within one or more rows being connected to circuitry in other rows by interconnects which are located in tracks. A track is a location on an integrated circuit die in which an interconnect may be placed, depending on a given design.
FIG. 2 depicts a typical layout of a prior art megablock showing power, ground, and possible track locations.
Referring to FIG. 2, megablock 30 comprises power conductors 32a through 32h provided therein to supply power to columns of bit slices 36a through 36h, and ground conductors 34a through 34h. In a typical megablock, each row such as rows 38 and 40 might have similar functional circuitry throughout each of the bit slices, with the functional circuitry in a given bit slice being connected to circuitry in a different row.
FIG. 3 depicts a prior art bit slice in any given row within a megablock.
Referring to FIG. 3, bit slice 40 comprises power conductor 42, ground conductor 44, dotted lines showing potential track locations 46, 48, and 50, and conductors 52 and 54. In a typical bit slice, there are many more signal paths which connect various functional blocks together in order to perform the intended function. However, only two signal paths are depicted herein in order to avoid needlessly over complicating the disclosure and drawings.
As circuit designs become more complex, and utilize higher and higher signal frequencies, the distance between conductors becomes an increasingly critical factor due to the possibility that signals on one conductor might be inductively or capacitively coupled-to one or more other conductors. For example, conductor 52 is adjacent to conductor 54, making it possible that a signal on conductor 54 might be unintentionally coupled to conductor 52, causing conductor 52 to act in a way which is not intended by the designer.
In order to understand how the prior art routes conductors so that unintended coupling between conductors is minimized, it is necessary to understand how integrated circuits are designed.
Typically, circuitry functionality is modeled in a high-level language such as Verilog. The model is then provided to an analyzer which determines the placement of functional blocks and the routing of circuitry, so that the intended design functions as modeled. Thus, although the designer determines the input and output conditions necessary for proper functionality of a system, the placement of conductors such as conductors 52 and 54 in a single bit slice such as depicted in FIG. 2 is determined using design rules. These design rules include details specifically associated with the manufacturing process which will be used to manufacture the IC.
One element of a design which is controllable, and which also affects the placement of conductors in a bit slice is whether a given signal path requires a “quiet” environment in which to operate. If a given signal path is required to be placed in an environment where inductive and capacitive coupling is minimized, the designer provides that information in the model supplied to the analyzer, and the analyzer takes appropriate action to maximize the coupling of the sensitive conductor to a constant signal source. The appropriate prior art action is to add a new conductor.
For example, in FIG. 4, critical conductor 52 has been placed by the analyzer in the location depicted, immediately adjacent to noisy conductor 54. A critical conductor is a conductor which is sensitive to the adjacent noisy conductor, wherein the adjacent noisy conductor is capable of being inductively coupled or capacitively coupled to the critical conductor. In order to minimize the coupling between conductor 52 and conductor 54, prior art analyzers route a third conductor 60 from a stable conductor, such as ground conductor 44, to a position adjacent to conductor 52.
This technique for routing a constant conductor is known to those of ordinary skill in the art to cause a sensitive conductor to partially couple to the constant conductor, thus minimizing the coupling of the sensitive conductor to the noisy conductor. However, this technique also mandates the use of an available track within a bit slice for the placement of the extra conductor, making the use of that track for other circuitry impossible. In order to provide enough silicon real estate to accomplish this technique in crowded bit slices, it is often necessary to design the wafer to allow for larger bit slices, an undesirable effect.
While the methods used in the prior art are effective for minimizing the inductive and capacitive coupling of noisy signal paths to sensitive signal paths, prior art methods suffer in that significant unnecessary use of silicon real estate results from those methods.
It would therefore be beneficial to provide a method for minimizing coupling of noisy conductors to sensitive conductors which utilizes less silicon real estate than the prior art.